Flip feram cell and method to form same

ABSTRACT

A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

DESCRIPTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a ferroelectric random accessmemory (FERAM) cell, and in particular to a method of fabricating aferroelectric (FE) capacitor on a complementary metal oxidesemiconductor (CMOS) structure wherein exposure of the integratedstructure to high temperature steps of FE deposition and processing iseliminated. The present invention also relates to a FERAM cell designand to a method to bond a FE capacitor to the CMOS structure afterfabrication of both structures is complete, thereby avoiding theincompatibilities between the two processes. The resulting structure canbe used as a non-volatile RAM (NVRAM) or a dynamic random access memory(DRAM), if the FE material is replaced with a material ofhigh-dielectric-constant.

[0003] 2. Background of the Invention

[0004] The integration of high value capacitors in integrated circuits(ICs) is limited by the fact that conventional high value capacitorstake up large areas of the IC chip, thus reducing device packing densityand layout efficiency. Many applications require a large number ofcapacitors. Often the capacitors must be incorporated as discreteoff-chip components, substantially increasing the bulk of the peripheralcircuitry. In view of the increasing demand for compact lightweightelectronic equipment, it is desirable that the number of discretecomponents be reduced.

[0005] The minimum dimensions of IC capacitors are determined primarilyby the relatively low dielectric constant (0<10) of conventionalcapacitor dielectrics, e.g. SiO₂ and Si₃N₄. Thus, as device dimensionsdecrease, there is increasing interest in other dielectrics havinghigher dielectric constants than conventional dielectric materials.

[0006] Ferroelectric (FE) and high-epsilon (HE) dielectrics (0=20 orgreater) have found application in random access memory (RAM) cellssince they provide for the formation of NVRAMs and DRAMs. Moreover, whenused as NVRAM, ferroelectric dielectrics advantageously provide lowvoltage programmability, fast access times and low power consumption.

[0007] FE materials pose several integration problems. In particular,most ferroelectric materials require high temperature post-depositionoxygen anneals (600° C. or above) to achieve properties desirable forstorage media. However, such high anneal temperatures can beincompatible with the CMOS devices already fabricated on the wafer.Furthermore, any subsequent forming gas or hydrogen anneals (highlydesirable for CMOS devices) degrade the ferroelectric material, thusrequiring additional high temperature oxygen anneals late in theprocessing sequence which in turn are detrimental to the CMOS circuitry.

[0008] In view of the above drawbacks with prior art methods ofintegrating ferroelectric capacitors with CMOS structures, there is acontinued need for developing a new and improved method which is capableof providing an integrated FE capacitor/CMOS structure withoutsubjecting the CMOS structure to high temperature steps that aretypically required in the prior art for ferroelectric processing.

SUMMARY OF THE INVENTION

[0009] The present invention provides a method of integrating a FEcapacitor with a CMOS structure which allows-the CMOS structure to avoidpotentially-detrimental high-temperature steps needed for FE depositionand processing. The invention likewise provides a method of integratinga plurality of FE capacitors with a plurality of CMOS structures.Specifically, the method of the present invention comprises the stepsof:

[0010] (a) forming a CMOS structure in electrical contact with aconductive electrode layer on its exposed top surface;

[0011] (b) separately providing a ferroelectric delivery wafer, saidferroelectric delivery wafer comprising a sacrificial release layerformed on a delivery substrate, a conductive layer formed on saidsacrificial release layer and a ferroelectric film formed on saidconductive layer, said ferroelectric film having an exposed outersurface;

[0012] (c) placing said exposed outer surface of said ferroelectric filmon the CMOS structure of-step (a), wherein said ferroelectric film is incontact with said conductive electrode layer;

[0013] (d) bonding, at a temperature of less than about 600EC, the outersurface of said ferroelectric film to said CMOS structure; and

[0014] (e) separating the sacrificial release layer from the bondedstructure.

[0015] It is noted that the conductive electrode layer of the CMOSstructure of step (a) may be patterned or unpatterned. Likewise, theconductive layer of the delivery wafer may also be patterned orunpatterned.

[0016] If not previously patterned, one or more of the conductive layersin the integrated FE capacitor/CMOS structure may optionally bepatterned. This optional patterning step occurs after step (e) above.

[0017] Another embodiment of the present method is to apply a surfacetreatment to the conductive electrode layer of the CMOS structure priorto conducting step (c). In yet another embodiment of the presentinvention, the method also includes a step of forming a passivatinglayer over the structure provided in step (e). In still a furtherembodiment of the present invention, the delivery wafer may include asecond conductive layer on top of the ferroelectric film. In thisembodiment of the invention, the second conductive layer may bepatterned or unpatterned. In another aspect of the present invention, anovel integrated FE/CMOS structure is provided wherein the storagecapacitor is constructed over all the transistors and wiring levels(excluding possibly any pad out structures) of the CMOS structure.Specifically, the novel integrated FE/CMOS structure of the presentinvention comprises:

[0018] a CMOS structure having at least one conductive layer and atleast one transistor; and

[0019] a ferroelectric storage capacitor formed on said CMOS structure,said ferroelectric storage capacitor comprising a bottom conductiveelectrode, a layer of ferroelectric film and a top conductive electrode,wherein said bottom conductive electrode of said capacitor is connectedto a terminal of said transistor through one or more conductive layersof said CMOS structure.

[0020] The present invention also provides a novel ferroelectricdelivery wafer which allows for fabricating an integrated FERAM cellwhile isolating the CMOS circuitry from high temperaturepost-FE-deposition anneals. That is, although high temperature annealsare used in forming the separate CMOS and ferroelectric structures, andbonding thereof, no such anneals are needed thereafter. Specifically,the ferroelectric delivery wafer of the present invention comprises acarrier substrate, a sacrificial release layer formed on said carriersubstrate, a conductive layer formed on said sacrificial release layer,and a ferroelectric film formed on said conductive layer. This structureis flipped onto a CMOS structure so that the ferroelectric film is incontact with a CMOS structure having an upper conductive electrodelayer. After conducting steps (a) and (e) above, an integrated FE/CMOSstructure in accordance with the present invention, is formed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIGS. 1(a)-(e) are cross-sectional views illustrating the variousprocessing steps that may be employed in one embodiment of the presentinvention. In this embodiment, the conductive layer of the ferroelectricdelivery wafer is not patterned, whereas the conductive electrode layerof the CMOS structure is patterned.

[0022] FIGS. 2(a)-(e) are cross-sectional views illustrating differentembodiments of the present invention. In FIGS. 2(a)-(b), neither theconductive layer of the FE delivery wafer nor the conductive layer ofthe CMOS structure is patterned prior to bonding. In FIGS. 2(c)-(d),only the conductive layer of the FE delivery wafer is patterned. In FIG.2(e)-(f), the conductive layers of both the FE and CMOS structures arepatterned. In FIGS. 2(g)-(h) and FIGS. 2(i)-(j), an unpatterned FEdelivery wafer containing an additional conductive layer is bonded to anunpatterned and patterned CMOS wafer.

DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention will now be described in more detail byreferring to the drawings that accompany the present application. Itshould be noted that in the accompanying drawings like referencenumerals are used for describing like and corresponding elements.

[0024] Reference is first made to FIG. 1(a) which shows one possibleCMOS structure that can be employed in the present invention. In thisfigure, the conductive electrode layer is patterned. In addition to apatterned conductive electrode layer in the CMOS structure, the presentinvention also contemplates a non-patterned conductive electrode layersuch as those shown in FIGS. 2(a), (c), and 2(g). Although descriptionis made to the structure shown in FIG. 1(a), it is noted herein thatother CMOS structures containing at least one transistor and at leastone conductive layer can be employed in the present invention.

[0025] Specifically, the CMOS structure shown in FIG. 1(a) comprises asemiconductor substrate 10 having diffusion regions, i.e. diffusedportions of the bitlines, 12 formed in the surface thereof. On top ofthe semiconductor substrate there are shown transistor regions 14 whichare in contact with the diffusion regions 12. The CMOS structure shownin FIG. 1(a) further comprises multiple wiring levels (or conductivelayers) 16 which are formed in dielectric layer 18. The upper wiringlevel (or conductive layer) 16 u is composed of a patterned conductiveelectrode layer and it forms the bottom electrode of the integratedFE/CMOS structure of the present invention. Between the transistorregions, there is shown bitline 20 and bitline contact 22. It isemphasized that even though the figure depicts a patterned conductiveelectrode layer as 16 u, the present invention also contemplates the useof a non-patterned conductive electrode layer 16 u, as shown in FIGS.2(a), 2(c) and 2(g).

[0026] The structure shown in FIG. 1(a) is composed of materials wellknown to those skilled in the art and it is fabricated usingconventional processes well known to those skilled in the art. Forexample, semiconductor substrate 10 is composed of any semiconductingmaterial including, but not limited to: Si, Ge, SiGe, GaAs, InAs, InP,all other III/V compounds and organic semiconductors. The semiconductorsubstrate may be doped or undoped. The diffusion regions may contain por n type dopants.

[0027] The transistor region is comprised of a conventional gate stackwhich includes a layer of gate insulator such as SiO₂ formed on thesurface of the semiconductor substrate and a layer of polysilicon orother gate conductor formed on the gate insulator. A salicide layer maybe formed on top of the polysilicon or gate conductor. Transistor region14 may be separated by sidewall isolation regions as well as otherconventional components well known to those skilled in the art. Forsimplicity, the various elements of the transistor are not shown in thedrawings, but are nevertheless intended to be included in region 14.

[0028] Wiring levels 16 comprise vias and lines which containconventional conductive materials such as metals, noble-metals,conductive nitrides, noble metal oxides, conductive oxides and mixturesor multilayers thereof. Exemplary conductive materials include: Cu, W,Al, Pt, polysilicon, TiN, Ta, TaN, Ti and WSi_(x). The various wiringlevels may be composed of the same or different conductive material. InFIG. 1(a), all the wiring levels (lines and vias) are depicted as beingcomposed of the same conductive materials.

[0029] Dielectric layer 18 is composed of any inorganic or organicdielectric material known to the art including, but not limited to:SiO₂, Si₃N₄, SiCOH, diamond-like carbon, paralyene polymers, polyimides,silicon-containing polymers, organic polymers, hybrid organo-siliconpolymers (HOSP) and other suitable dielectric materials. Dielectriclayer 18 may be composed of layers of the same material, shown in FIG.1(a), or layers of different dielectric materials (not shown). Whenlayers of different dielectric materials are used, a barrier layer, notshown in the drawings, may be formed between each successive wiringlevel. The optional barrier layer is composed of conventional materialsincluding, but not limited to: SiO₂, Al₂O₃, TiO₂, Si₃N₄, SiO_(x)N₄ andTa₂O₅.

[0030] As stated above, the structure shown in FIG. 1(a) is fabricatedusing conventional processing steps which are well known to thoseskilled in the art including: semiconductor device fabrication and backend of the line (BEOL) processing. For example, the CMOS device shown inFIG. 1(a) can be fabricated by forming the transistor region on thesurface of the semiconductor substrate, i.e. growing a gate insulator,depositing a gate conductor on said gate insulator and thereafterpatterning those layers to provide the transistor region. The diffusionregions can then be formed using conventional ion implantation andannealing.

[0031] Although the drawings of the present invention depict doing allBEOL wiring before bonding the wafers, it is also within thecontemplation of the present invention to carry out wiring afterbonding.

[0032] The wiring levels of the CMOS structure shown in FIG. 1(a) arethen typically formed by: depositing a dielectric material on thesurface of the semiconductor structure, opening vias in the dielectriclayer, filling the vias with a conductive material, forming trenches inthe dielectric layer over the vias, filling the trenches with aconductive material, and planarizing the structure using conventionalplanarization techniques such as chemical-mechanical polishing orgrinding. It is noted that in this figure, the last. i.e. upper, wiringlevel 16 u is a patterned conductive electrode comprising a conductiveelectrode material. The conductive electrode layer 16 u is the bottomelectrode of the integrated FE/CMOS structure of the present invention.

[0033] Suitable conductive electrode materials that can be used in thepresent invention as the upper conductive layer of the CMOS structureinclude, but are not limited to: noble metals such as Pt, Pd, Ir, Rh,Os, Au, Ag, and Ru; noble metal oxides such as PtO_(x), IrO_(x),,PdO_(x), RhO_(x), OsO_(x), AuO_(x), AgO_(x) and RuO_(x); conductingoxides such as SrRuO₃, LaSrCoO₃, YBa₂Cu₃O₇; non-noble metals; conductingsilicides; doped polycrystalline silicon; mixtures and multilayersthereof. The noble metals and/or oxides may be crystalline or in anamorphous form. As stated above, the upper conductive electrode layer ofthe CMOS structure may be patterned using conventional lithography andRIE or unpatterned.

[0034] The upper conductive layer of the CMOS structure may furtherinclude an additional layer of a consumable material which cansubsequently react with one or more layers of the ferroelectric deliverywafer during bonding. This consumable layer may be conductive,semiconducting, or insulating, and patterned before or after said stepof bonding. The consumable layer is preferably formed from a materialsuch as doped or undoped polycrystalline silicon which may react with ametal layer to form a conductive metal silicide.

[0035] It is noted that bitline and bitline contacts, 20 and 22respectively, are composed of conductive materials and may be fabricatedin the same manner as the various wiring levels.

[0036] After forming the conductive electrode layer 16 u, which mayinclude planarization, the structure may optionally be subjected to anappropriate surface treatment step. Suitable surface treatments that mayoptionally be employed in the present invention include: oxidation byplasma ashing, thermal oxidation, surface chemical treatments andapplication of a thin metal oxide layer by chemical solution deposition(CSD), chemical vapor deposition (CVD) or physical vapor deposition(PVD).

[0037] When oxidation by plasma ashing is performed, it may be carriedout using high density plasma, microwave plasma, RF plasma ion beambombardment produced by an oxygen-containing ion beams, or combinationthereof, with or without separately controllable biasing. Typically,when employed, plasma ashing is conducted in a reaction chamber havingan oxygen pressure between about 0.01 to about 2000 mTorr, a radiofrequency power of at least 50 W and an exposure time of at least 1second.

[0038] When thermal oxidation is employed as the surface treatmentmeans, the oxidation is typically carried out a temperature of less thanabout 600EC. The thermal oxidation may include: HCl, H₂O or H₂O₂ toenhance hydroxyl formation. Suitable oxidizing gases include: O₂, N₂O,O₃ or combination thereof.

[0039] When surface chemical treatments are employed as the optionalsurface treatment means, acids such as HNO₃, H₂SO₄ and aqua regia;bases; and peroxide washes may be employed.

[0040] In accordance with the present invention, a ferroelectricdelivery wafer is prepared separately from the CMOS structure shown inFIG. 1(a). One possible ferroelectric delivery wafer of the presentinvention is shown in FIG. 1(b). Specifically, the delivery wafercomprises a carrier substrate 24, a sacrificial release layer 26 formedon said carrier substrate, a conductive layer 28 formed on thesacrificial release layer, and a ferroelectric film 30 formed on theconductive layer. The conductive layer 28 may be patterned as shown in2(d) and 2(f) or non-patterned as shown in FIG. 1(b), 2(b), 2(h) and2(j). If patterned, conductive layer 28 of FIG. 2(f) is preferablyembedded in dielectric layer 29 to insure planarity of the ferroelectricdelivery wafer. In another embodiment of the present invention, anoptional second conductive layer 34 is formed on the, ferroelectric filmas shown in FIGS. 2(h) and 2(j).

[0041] A suitable anneal may be performed at this time to achievedesired ferroelectric properties. Typically, such an anneal is carriedout at a temperature of about 600° C. or above.

[0042] Carrier substrate 24 may be composed of one of the semiconductingmaterials described for semiconductor substrate 10 or it may be composedof a dielectric material like the kind mentioned above for dielectriclayer 18. The carrier substrate could also be a material with itsthermal-expansion coefficient well-matched to Si. Some ceramics exhibitthis property. Likewise, conductive layer 28, which forms the topelectrode of the capacitor of the present invention, and the optionalsecond conductive layer 34 comprise one or more of the previouslymentioned metals, noble metals, conductive nitrides, noble metal oxides,conductive oxides, conducting silicides, doped polycrystalline silicon,mixtures and multilayers thereof, which are used in forming conductivelayers 16 in the CMOS structure.

[0043] Second conductive layer 34 of the ferroelectric delivery wafermay further include an additional layer of a consumable material whichcan subsequently react with one or more layers of the CMOS structureduring bonding. This consumable layer may be conductive, semiconducting,or insulating, and patterned before or after said step of bonding. Theconsumable layer is preferably formed from a material such as doped orundoped polycrystalline silicon which may react with a metal layer toform a conductive metal silicide. While a consumable bonding layer maybe present on either the ferroelectric delivery wafer or the CMOSstructure prior to bonding, a preferable embodiment comprises anoxidation-resistant silicide-forming metal such as Pt or Ir as theoptional second conductive material of the ferroelectric delivery wafer,and a thin (5-50 nm) consumable polycrystalline silicon layer on theCMOS structure.

[0044] Sacrificial release layer 26 may be an etch stop layer (for thesituation in which the delivery wafer substrate is removed by etching).It may also be a surface layer of the delivery substrate that has beenion-implanted (before or after the ferroelectric deposition) withspecies such as hydrogen that become volatile upon heating. It may alsobe a deposited layer that is preferably thermally stable at theferroelectric decomposition temperature, and easily selectively etchedor decomposed without damage to the ferroelectric or conductive layers.Suitable deposited sacrificial release layers include, but are notlimited to: GeO₂, W, TiN, IrO₂ PdO, and WSi₂.

[0045] Sacrificial release layer 26 may further include an optionalpassivation layer to protect the transferred layers against the damagingconditions of the releasing process. This optional layer would typicallybe transferred with the ferroelectric and electrode layers, and be usedin cases where the release process entailed exposure to hydrogen orother reducing species. Optional passivation layer materials include:Al₂O₃, TiO₂, Ta₂O₅, Si₃N₄, and SiO₂.

[0046] The ferroelectric film that is employed as element 30 of thedelivery element of the present invention is a crystalline,polycrystalline or amorphous high dielectric constant material (0=20 orabove). Suitable ferroelectric materials that can be employed in thepresent invention include, but are not limited to: the perovskite-typeoxides, layered ferroelectrics, compounds containing pyrochlorestructures such as Cd₂Nb₂O₇, potassium dihydrogen phosphates, phosphatesof rubidium, cesium or arsenic and other like ferroelectric materials.Combinations of these ferroelectric materials or multilayers are alsocontemplated herein. High-epsilon materials may also be employed in thepresent invention as the high dielectric ferroelectric material. Thehigh dielectric material may display a spontaneous electric polarization(for NVRAM) or not (DRAM).

[0047] Of the aforementioned ferroelectric materials, it is highlypreferred that the ferroelectric film of the present invention becomposed of a perovskite-type oxide. The term Aperovskite-type oxide@ isused herein to denote a material which includes at least one acidicoxide containing at least one metal from Group IVB (Ti, Zr or Hf), VB(V, Nb or Ta), VIB (Cr, Mo or W), VIIB (Mn or Re), IIIA (Al, Ga or In)or IB (Cu, Ag or Au) of the Periodic Table of Elements (CAS version) andat least one additional cation having a positive formal charge of fromabout 1 to about 3. Such perovskite-type oxides typically have the basicformula: ABO₃ wherein A is one of the above mentioned cations, and B isone of the above mentioned metals which forms the acidic oxide.

[0048] Suitable perovskite-type oxides include, but are not limited to:titanate-based ferroelectrics, manganate-based materials, cuprate-basedmaterials, tungsten bronze-type niobates, tantalates, or titanates, andbismuth layered-tantalates, niobates or titanates. Of theseperovskite-type oxides, it is preferred to use strontium bismuthtantalate, strontium bismuth niobate, bismuth titanate, strontiumbismuth tantalate niobate, lead zirconate titanate, lead lanthanumzirconate titanate, and compositions of these materials modified by theincorporation of dopants as the ferroelectric material.

[0049] The ferroelectric wafer structure shown in FIG. 1(b) is formedusing conventional deposition processes well known to those skilled inthe art. For example, layers 26 and 28 of the delivery wafer may beformed by chemical vapor deposition (CVD), plasma-assisted CVD,sputtering, reactive sputtering, pulsed-laser deposition, chemicalsolution deposition, physical-vapor deposition, plating and other likedeposition techniques. After deposition of each layer, the structure mayoptionally be planarized using conventional techniques such aschemical-mechanical polishing.

[0050] The ferroelectric film is also formed using conventionaldeposition techniques well known to those skilled in the art including,but not limited to: chemical solution deposition (CSD), sol gel,metal-organic decomposition, spin coating, sputtering, reactivesputtering, metal-organic chemical vapor deposition, physical vapordeposition, plasma-assisted chemical vapor deposition, pulsed laserdeposition, chemical vapor deposition, evaporation and like depositiontechniques. A high temperature anneal may need to be performed at thistime to obtain desired ferroelectric properties.

[0051] After forming the structure shown in FIG. 1(b), the ferroelectricdelivery wafer is placed in proximity to the CMOS structure of FIG. 1(a)so that ferroelectric film 30 is in contact with patterned conductiveelectrode layer 16 u and the top surface of dielectric layer 18. Thisintermediate structure is shown in FIG. 1(c).

[0052] In one embodiment of the present invention, the ferroelectricdelivery wafer is optionally treated with one of the above mentionedsurface treatments prior to bonding. In embodiments wherein a patternedconductive layer is employed in the delivery wafer, an alignment processmay be necessary to ensure proper placement of the delivery wafer on theCMOS structure.

[0053] The intermediate structure of FIG. 1(c) is then bonded at atemperature of less than about 600° C. so that bonding occurs betweenferroelectric film 30 and the top dielectric layer of the CMOS structureas well as patterned conductive electrode layer 16 u. Specifically, theannealing step is carried out in a substantially inert gas atmosphere,e.g. vacuum, He, Ar, N₂, or mixtures thereof that can be optionallymixed with an oxidizing gas such as O₂, steam, O₃, N₂O or H₂O₂. Highlypreferred annealing temperatures that can be employed in the presentinvention are from about room temperature, i.e. 25EC, to about 600EC,with from about 100° to about 400° C. being more highly preferred.Typically, annealing is carried out for a time period of from about 1minute to about 6 hours, with from about 2 minutes to about 3 hoursbeing more highly preferred. The annealing step may be carried out usinga single ramp cycle or multiple ramp and soak cycles can also be used.

[0054] Bonding may be additionally facilitated using external pressureto push the bonding interfaces together, and/or by using the surfacetension of a thin, removable liquid layer placed at the bondinginterface. The thin liquid layer would typically be water, and could beremoved by evaporation. Bonding may also be facilitated with the use ofelectric fields in processes known to the prior art as anodic bonding.

[0055] After bonding ferroelectric film 30 to the CMOS structure,sacrificial release layer 26 and carrier substrate 24 are removed fromthe structure, See FIG. 1(d). The preferred method for removing thecarrier substrate depends on the type of sacrificial release layerselected. One means of removing the carrier wafer is by a selective etchprocess.

[0056] It is noted that in this figure, the ferroelectric film is bondedto the CMOS dielectric and the upper conductive electrode layer. Inaccordance with the present invention, the upper conductive electrodelayer 16 u of the CMOS structure becomes the bottom electrode of thestorage capacitor. On top of the ferroelectric film is the upperelectrode 28 of the capacitor. As further shown in FIG. 1(d), thecapacitor, i.e. upper conductive electrode layer (bottom electrode) 16u, ferroelectric film 30 and conductive layer (upper electrode) 28, isformed over the CMOS structure. In cases wherein the conductiveelectrode layer 16 u of the CMOS is not patterned in FIGS. 2(a), 2(c)and 2(g), ferroelectric film 30 would be directly bonded to theunpatterned conductive layer. In cases where the optional conductivelayer is present on the FE delivery wafer, the optional conductive layerwould be bonded to the CMOS wafer.

[0057] After removing at least most of the carrier substrate 24 and thesacrificial release film 26, the resulting integrated CMOS/FE structuremay be optionally polished. Additional electrode and/or ferroelectricpatterning steps may then be performed as required for electricalisolation of individual capacitor elements. A passivating material 32,as shown in FIG. 1(e), may then be optionally formed on the surface ofconductive layer 28. Suitable passivating materials include: Al₂ ₃,TiO₂, Ta₂O₅, Si₃N₄ and SiO₂. The passivating material layer is formedusing conventional deposition processes well known to those skilled inthe art including, but not limited to: CVD, dip coating and spin-oncoating. The thickness thereof is sufficient to prevent diffusion of airor moisture into the underlying layers of the integrated FE/CMOSstructure.

[0058] While the present invention has been particularly shown anddescribed with respect to preferred embodiments thereof, it will beunderstood by those skilled in the art that the foregoing and otherchanges in form and detail may be made without departing from the spiritand scope of the present invention.

Having thus described our invention, what we claim as new and desire tosecure by the Letters Patent is:
 1. A method of fabricating anintegrated FE/CMOS structure comprising the steps of: (a) forming a CMOSstructure in electrical contact with a conductive electrode layer; (b)separately providing a ferroelectric delivery wafer, said ferroelectricdelivery wafer comprising a sacrificial release layer formed on adelivery substrate, a conductive layer formed on said sacrificialrelease layer and a ferroelectric. film formed on said conductive layer,said ferroelectric film having an exposed outer surface; (c) placingsaid exposed outer surface of said ferroelectric film on the CMOSstructure of step (a), wherein said ferroelectric film is in contactwith said conductive electrode layer; (d) bonding, at a temperature ofless than about 600 □C., the outer surface of said ferroelectric film tosaid CMOS structure; and (e) separating the sacrificial release layerfrom the bonded structure.
 2. The method of claim 1 further comprising:(f) optionally performing additional steps required for electricalisolation of individual capacitor elements.
 3. The method of claim 1wherein a passivating layer is formed over the structure provided instep (e).
 4. The method of claim 1 wherein said conductive electrodelayer of said CMOS structure is patterned or unpatterned.
 5. The methodof claim 1 wherein said conductive layer of said ferroelectric deliverywafer is patterned or unpatterned.
 6. The method of claim 1 furthercomprising a surface treatment step to said conductive electrode layerand/or said ferroelectric film prior to step (c).
 7. The method of claim1 wherein said delivery wafer of step (c) further includes a secondconductive layer over said ferroelectric film, and said placing andbonding of steps (c) and (d) entails the exposed outer surface of saidsecond conductive layer instead of said FE layer.
 8. The method of claim7 wherein said second conductive layer is patterned before or after saidstep of bonding.
 9. The method of claim 1 wherein said CMOS structurefurther comprises a transistor region formed on top of a semiconductorsubstrate.
 10. The method of claim 9 wherein said semiconductorsubstrate is a semiconducting material selected from the groupconsisting of Si, Ge, SiGe, GaAs, InAs, InP, other III/V compounds andorganic semiconductors.
 11. The method of claim 1 wherein said carriersubstrate is a semiconducting material or a dielectric material.
 12. Themethod of claim 1 wherein said conductive electrode layer of said CMOSstructure is composed of a conductive material selected from the groupconsisting of a metal, a noble metal, a noble metal oxide, a conductiveoxide, a conductive nitride, a conductive suicide, a dopedpolycrystalline silicon, and mixtures and multilayers thereof.
 13. Themethod of claim 12 wherein said conductive layer further includes aconsumable reaction layer which may be conductive or non-conductive. 14.The method of claim 13 wherein said consumable reaction layer iscomposed of doped or undoped polycrystalline silicon.
 15. The method ofclaim 1 wherein said conductive layer of said ferroelectric deliverywafer is composed of a metal, a noble metal, a noble metal oxide, ormixtures and multilayers thereof.
 16. The method of claim 7 wherein saidconductive layer of said delivery wafer is composed of a conductivematerial selected from the group consisting of a metal, a noble metal, anoble metal oxide, a conductive oxide, a conductive nitride, aconductive silicide, doped polycrystalline silicon, and mixtures andmultilayers thereof.
 17. The method of claim 7 wherein said secondconductive layer of said delivery wafer further includes a consumablereaction layer which may be conductive or non-conductive.
 18. The methodof claim 17 wherein said consumable reaction layer is composed of dopedor undoped polycrystalline silicon.
 19. The method of claim 1 whereinsaid ferroelectric film is selected from the group consisting of aperovskite-type oxide, a layered ferroelectric, a compound containing apyrochlore structure, potassium dihydrogen phosphate and a phosphate ofrubidium, cesium or arsenic.
 20. The method of claim 19 wherein saidferroelectric material is a perovskite-type oxide having the formulaABO₃ wherein B is at least one acidic oxide containing a metal fromGroup IVB, VB, VIB, IIIA, VIIB or IB of the Periodic Table of Elements,and A is at least one additional cation having a positive formal chargeof from about 1 to about
 3. 21. The method of claim 20 wherein saidperovskite-type oxide is a titanate-based ferroelectric, amanganate-based material, a cuprate based material, a tungstenbronze-type niobate, tantalate or titanate, or a layered bismuthtantalate, niobate or titanate.
 22. The method of claim 21 wherein saidferroelectric film is composed of a ferroelectric material selected fromthe group consisting of bismuth titanate, strontium bismuth tantalate,strontium bismuth niobate, strontium bismuth tantalate niobate, leadzirconate titanate, lead lanthanum zirconate titanate and compositionsof these materials modified by incorporation of a dopant.
 23. The methodof claim 1 wherein step (d) is carried out in vacuum or in asubstantially inert gas atmosphere, said inert gas atmosphere beingselected from the group consisting of He, Ar, N₂, and mixtures thereof.24. The method of claim 1 wherein step (d) is carried out at atemperature of from about 25° to about 600° C. for a time period of fromabout I minute to about 6 hours.
 25. The method of claim 24 wherein step(d) is carried out at a temperature of from about 100° to about 400° C.for a time period of from about 2 minutes to about 3 hours.
 26. Themethod of claim 1 wherein said sacrificial release layer is selectedfrom the group consisting of GeO₂, W, TiN, IrO₂, PdO and WiSi₂.
 27. Themethod of claim 1 wherein said sacrificial release layer of step (b) isprovided by implanting said delivery wafer with a desorbable speciesprior to or after deposition of said ferroelectric layer.
 28. The methodof claim 27 wherein said desorbable species is hydrogen.
 29. Anintegrated FE/CMOS structure comprising a CMOS structure having at leastone conductive layer and a transistor; and a ferroelectric storagecapacitor formed on said CMOS structure, said ferroelectric storagecapacitor comprising a bottom conductive electrode, a layer offerroelectric film and a top conductive electrode, wherein said bottomconductive electrode of said capacitor is connected to a terminal ofsaid transistor through one or more of said conductive layers of saidCMOS structure.
 30. The integrated FE/CMOS structure of claim 29 whereinsaid CMOS structure further includes a semiconductor substrate.
 31. Theintegrated FE/CMOS structure of claim 30 wherein said semiconductorsubstrate is a semiconducting material selected from the groupconsisting of Si, Ge, SiGe, GaAs, InAs, InP, other III/V compounds, andorganic semiconductors.
 32. The integrated FE/CMOS structure of claim 29wherein said top and bottom conductive electrodes are composed of thesame or different conductive materials, said conductive materials areselected from the group consisting of metals, noble metals, noble metaloxides, conductive oxides, conductive nitrides, doped polycrystallinesilicon, conductive metal silicides and mixtures or multilayers thereof.33. The integrated FE/CMOS structure of claim 29 wherein saidferroelectric film is selected from the group consisting of aperovskite-type oxide, a layered ferroelectric, a compound containing apyrochlore structure, potassium dihydrogen phosphate and a phosphate ofrubidium, cesium or arsenic.
 34. The integrated FE/CMOS structure ofclaim 33 wherein said ferroelectric material is a perovskite-type oxidehaving the formula ABO₃ wherein B is at least one acidic oxidecontaining a metal from Group IVB, VB, VIB, VIIB, IIIA or IB of thePeriodic Table of Elements, and A is at least one additional cationhaving a positive formal charge of from about 1 to about
 3. 35. Theintegrated FE/CMOS structure of claim 34 wherein said perovskite-typeoxide is a titanate-based ferroelectric, a manganate-based material, acuprate based material, a tungsten bronze-type niobate, tantalate ortitanate, or a layered bismuth tantalate, niobate or titanate.
 36. Theintegrated FE/CMOS structure of claim 35 wherein said ferroelectric filmis composed of a ferroelectric material selected from the groupconsisting of bismuth titanate, strontium bismuth tantalate, strontiumbismuth niobate, strontium bismuth tantalate niobate, lead zirconatetitanate, lead lanthanum zirconate titanate and compositions of thesematerials modified by incorporation of a dopant.
 37. The integratedFE/CMOS structure of claim 29 wherein said top and bottom electrodes arepatterned or unpatterned.
 38. A FE delivery wafer comprising a carriersubstrate, a sacrificial release layer formed on said carrier substrate,a conductive layer formed on said sacrificial release layer and aferroelectric film formed on said conductive layer.
 39. The FE deliverywafer of claim 38 wherein said carrier substrate is a semiconductingmaterial or a dielectric material.
 40. The FE delivery wafer of claim 39wherein said semiconducting material is Si, Ge, SiGe, GaAs, InAs, InP,another III/V compound or an organic semiconductor.
 41. The FE deliverywafer of claim 39 wherein said dielectric material is an inorganic ororganic dielectric material selected from the group comprising SiO₂,Si₃N₄, SiCOH, diamond-like carbon, paralyene polymers, polyimides andsilicon-containing polymers, organic polymers, and hybrid organo-siliconpolymers (HOSP).
 42. The FE delivery wafer of claim 38 furthercomprising a second conductive layer formed on said ferroelectric film.43. The FE delivery wafer of claim 38 wherein said ferroelectric film iscomposed of a perovskite-type oxide, a layered ferroelectric, a compoundcontaining a pyrochlore structure, potassium dihydrogen phosphate or aphosphate of rubidium, cesium or arsenic.
 44. The FE delivery wafer ofclaim 43 wherein said ferroelectric material is a perovskite-type oxidehaving the formula ABO₃ wherein B is at least one acidic oxidecontaining a metal from Group IVB, VB, VIB, VIIB, IIIA or IB of thePeriodic Table of Elements, and A is at least one additional cationhaving a positive formal charge of from about 1 to about
 3. 45. The FEdelivery wafer of claim 44 wherein said perovskite-type oxide is atitanate-based ferroelectric, a manganate-based material, a cupratebased material, a tungsten bronze-type niobate, tantalate or titanate,or a layered bismuth tantalate, niobate or titanate.
 46. The FE deliverywafer of claim 45 wherein said ferroelectric film is composed of aferroelectric material selected from the group consisting of bismuthtitanate, strontium bismuth tantalate, strontium bismuth niobate,strontium bismuth tantalate niobate, lead zirconate titanate, leadlanthanum zirconate titanate and compositions of these materialsmodified by incorporation of a dopant.
 47. The FE delivery wafer ofclaim 38 wherein said sacrificial release layer selected from the groupconsisting of GeO₂, W, TiN, IrO₂, PdO and WSi₂.
 48. The FE deliverywafer of claim 38 wherein said sacrificial release layer is provided byimplanting said delivery wafer with a desorbable species prior to orafter deposition.
 49. The FE delivery wafer of claim 48 wherein saiddesorbable species is hydrogen.
 50. The FE delivery wafer of claim 38wherein said conductive layer is patterned or non-patterned.